1. Field of the Invention
This invention relates to an active matrix display apparatus having a storage capacity.
2. Description of the Prior Art
An active matrix system of the type having pixel electrodes arranged in a matrix fashion on an insulating substrate so that the pixel electrodes are independently driven has been employed in display apparatuses using liquid crystals. Such an active matrix system has often been employed especially in large-sized display apparatuses geared for high-density display.
Thin film transistor (TFT) apparatuses, MOS transistor devices, MIM (metal - insulator - metal) devices, diodes, varistors, and the like have been used as switching devices for selectively driving the pixel electrodes. An active matrix drive system affords high contrast display and indeed it has been put into practical use in various areas of application, including liquid crystal television, word processors, and terminal display units for computers.
FIG. 4 shows a plan view of a conventional active matrix display apparatus, which includes an active matrix board 1 and a counter substrate 2 placed upon the board 1. In this display apparatus, TFTs are used as switching devices. A display medium, such as a liquid crystal, is contained in the space between the active matrix board 1 and the counter substrate 2 to thereby form the display apparatus.
FIG. 5 schematically illustrates the active matrix board 1 shown in FIG. 4. The active matrix board 1 comprises gate bus lines 7, source bus lines 9, intersecting the gate bus lines 7, and storage capacitance lines (i.e., addition capacitance lines) 8 arranged in a parallel relation to the gate bus lines 7. All the storage capacitance lines 8 are connected to a common main line 6 for storage capacitances. As shown in FIG. 4, in portions of the active matrix board 1 which are not covered by the counter substrate 2 placed on the board 1 there are arranged source signal terminals 3a, 3b, gate signal terminals 4, and common line terminals 5a, 5b connected to the common main line 6.
FIG. 2 is a schematic diagram showing a rectangular area surrounded by source bus lines 9, a gate bus line 7 and a storage capacitance line 8 as are shown in FIG. 5. A gate electrode 21 of a TFT 10 is connected to the gate bus line 7, and a source electrode 22 of the TFT 10 is connected to one of the source bus lines 9. A drain electrode 23 is connected to a pixel electrode 11. A storage capacitance 12 is formed between a storage capacitance electrode (i.e., an addition capacitance electrode) 24 connected to the storage capacitance line 8 and the pixel electrode 11.
In this display apparatus, when an ON signal is applied to the gate bus line 7, the resistance of the TFT 10 is lowered and a data signal output to the one source bus line 9 is written to the pixel electrode 11. Upon completion of writing of the data, an OFF signal is applied to the gate bus line 7 and the resistance of the TFT 10 becomes higher. The data signal written is held by the storage capacitance 12 between the pixel electrode 11 and the storage capacitance electrode 24 and also by a pixel capacitance between the pixel electrode 11 and a counter electrode (not shown) on the counter substrate 2. The data signal is retained in place until the next writing takes place.
Each gate bus line 7, each source bus line 9, and each storage capacitance line 8 are made of metal or other conductive materials and respectively have electric resistances R (G), R (S), and R (Cs). These lines 7, 9 and 8 respectively have capacitances C (G), C (S), and C (Cs) formed between the individual lines 7, 9 and 8 as one part and other individual intersecting lines and counter electrodes as the other part. Therefore, on the respective lines 7, 9 and 8 there will occur signal delays corresponding to time constants .tau. (G), .tau. (S), .tau. (Cs) represented by products of the respective resistances and the respective capacitances. Because of such signal delay, a signal applied to the terminal of each respective line will delay as it advances toward the leading end of the line.
The magnitude of such a signal delay depends upon time constants .tau. (G) and .tau. (S) on the gate bus line 7 and source bus line 9 respectively, where a signal delay on the storage capacitance line 8 depends on the value of .tau. (Cs) added by .tau. (Cs .sub.0) on the common main line 6. Since all storage capacitance lines 8 are connected to the common main line 6, the value of .tau. (Cs .sub.0) is an enormous one. Therefore, a signal applied to common line terminals 5a and 5b will delay on the common main line 6 and further delay on the storage capacitance line 8.
In the active matrix board shown in FIG. 5, a signal delay on the common main line 6 is greatest at a central part of the line 6 which is most remote from the common line terminals 5a and 5b. A signal delay on the storage capacitance line 8 is largest at a portion of the line 8 which is most remote from the common main line 6. In the example shown in FIG. 5, therefore, a signal delay is largest at a central portion of the board at the right end thereof. Data signals cannot always satisfactorily be written to the pixel electrode 11 connected to the portion of the storage capacitance line 8 at which a large signal delay occurs while an ON signal is being applied to the gate bus line 7. Thus, a display irregularity due to the signal delay may occur on the display.
As the display screen becomes larger, line resistance and line capacitance become greater and accordingly the above-mentioned problems will more conspicuously occur. Similarly, as the display screen becomes more refined, a greater number of lines are involved and accordingly such problems will become more conspicuous.
For instance, a trial calculation can be made with respect to a liquid crystal display apparatus having a diagonal of the order of 14 inches. Assuming that the material of the common main line 6 is Ti metal (with a specific resistance of 10.sup.-4 .OMEGA.. cm) and that the line 6 is 4000 .ANG. in thickness, 2 mm in width, and 200 mm in length, the resistance over the entire length of the common main line 6 is about 250 .phi.. Since the capacitance of the common main line 6 is more than 0.2.mu. F, the time constant at the center portion of the common main line 6 at which the signal delay is greatest is more than 12.5.mu. sec. In a display apparatus in which 480 bus lines are subjected to non-interlace scanning, the required write time for a data signal is about 30.mu. sec. It can be understood from this that the above-mentioned time constant value is unacceptably large. Therefore, the display apparatus is subject to considerable display irregularities.